Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the
corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either
no interrupt has been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIMis set), an interrupt
for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event
Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion
is initiated. See page 566.
If no other Port B pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0)
register can disable the Port B interrupts, and the ADC interrupt can be used to read back the
converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts on PB4and
wait for the ADC interrupt, or the ADC interrupt must be disabled in the EN0 register and the Port
B interrupt handler must poll the ADC registers until the conversion is completed. See page 112 for
more information.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
Offset 0x418
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
427July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
