Table 9-4. GPIO Pad Configuration Examples (continued)
GPIO Register Bit Value
a
Configuration
SLRDR8RDR4RDR2RPDRPURDENODRDIRAFSEL
??????10X1Digital Input/Output
(UART)
XXXX000000Analog Input
(Comparator)
??????10X1Digital Output
(Comparator)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 9-5. GPIO Interrupt Configuration Example
Pin 2 Bit Value
a
Desired Interrupt
Event Trigger
Register
01234567
XX0XXXXX0=edge
1=level
GPIOIS
XX0XXXXX0=single edge
1=both edges
GPIOIBE
XX1XXXXX0=Low level, or falling
edge
1=High level, or rising
edge
GPIOIEV
001000000=masked
1=not masked
GPIOIM
a. X=Ignored (don’t care bit)
9.4 Register Map
Table 9-7 on page 418 lists the GPIO registers. Each GPIO port can be accessed through one of
two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible
with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers
the same register map but provides better back-to-back access performance than the APB bus.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to unconnected bits has no effect, and reading unconnected bits returns
no meaningful data.
The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s
base address:
■ GPIO Port A (APB): 0x4000.4000
■ GPIO Port A (AHB): 0x4005.8000
■ GPIO Port B (APB): 0x4000.5000
■ GPIO Port B (AHB): 0x4005.9000
■ GPIO Port C (APB): 0x4000.6000
■ GPIO Port C (AHB): 0x4005.A000
■ GPIO Port D (APB): 0x4000.7000
■ GPIO Port D (AHB): 0x4005.B000
417July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.