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LM3S6G65-IQC80-A2T

LM3S6G65-IQC80-A2T首页预览图
型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
  • LM3S6G65-IQC80-A2T PDF在线浏览
功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
GPIO Interrupt Both Edges (GPIOIBE) register (see page 423)
GPIO Interrupt Event (GPIOIEV) register (see page 424)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 425).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 426 and page 427). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates
that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the
interrupt controller.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 429).
When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts
should be masked (GPIOIM cleared). Writing any value to an interrupt control register can generate
a spurious interrupt if the corresponding bits are enabled.
9.2.2.1 ADC Trigger Source
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIMis set), an interrupt
for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event
Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion
is initiated. See page 566.
If no other Port B pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0)
register can disable the Port B interrupts, and the ADC interrupt can be used to read back the
converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts on PB4and
wait for the ADC interrupt, or the ADC interrupt must be disabled in the EN0 register and the Port
B interrupt handler must poll the ADC registers until the conversion is completed. See page 112 for
more information.
9.2.3 Mode Control
The GPIO pins can be controlled by either software or hardware. Software control is the default for
most signals and corresponds to the GPIO mode, where the GPIODATA register is used to read
or write the corresponding pins. When hardware control is enabled via the GPIO Alternate Function
Select (GPIOAFSEL) register (see page 430), the pin state is controlled by its alternate function
(that is, the peripheral).
Further pin muxing options are provided through the GPIO Port Control (GPIOPCTL) register which
selects one of several peripheral functions for each GPIO. For information on the configuration
options, refer to Table 21-5 on page 948.
Note: If any pin is to be used as an ADC input, the appropriate bit in the GPIOAMSEL register
must be set to disable the analog isolation circuit.
9.2.4 Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD
pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 430), GPIO Pull Up Select (GPIOPUR) register (see page 436), GPIO Pull-Down
Select (GPIOPDR) register (see page 438), and GPIO Digital Enable (GPIODEN) register (see
415July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
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