Table 9-3. GPIO Pins and Alternate Functions (108BGA) (continued)
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
a
Analog
Function
PinIO
1110987654321
-CCP3------PWM1IDX1--H12PF1
-------PWM2-PWM4LED1-J11PF2
-------PWM3-PWM5LED0-J12PF3
-------PWM4I2C1SCLPWM0U2Rx-K1PG0
-------PWM5I2C1SDAPWM1U2Tx-K2PG1
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin.
9.2 Functional Description
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
9-1 on page 412 and Figure 9-2 on page 413). The LM3S6G65 microcontroller contains seven ports
and thus seven of these physical GPIO blocks. Note that not all pins may be implemented on every
block. Some GPIO pins can function as I/O signals for the on-chip peripheral modules. For information
on which GPIO pins are used for alternate hardware functions, refer to Table 21-5 on page 948.
Figure 9-1. Digital I/O Pads
Pad
Control
Commit
Control
Mode
Control
GPIOAFSEL
Data
Control
Interrupt
Control
MUX
MUX
DEMUX
Digital
I/O
Pad
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Pad Input
Pad Output
Enable
GPIOLOCK
GPIOCR
GPIODATA
GPIODIR
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Package I/O Pin
MUX
Periph 0
Periph 1
Periph n
Port
Control
GPIOPCTL
July 24, 2012412
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
OBSOLETE: TI has discontinued production of this device.
