Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504
Each bit of the DMACHIS register represents the corresponding µDMA channel. A bit is set when
that μDMA channel causes a completion interrupt. The bits are cleared by a writing a 1.
DMA Channel Interrupt Status (DMACHIS)
Base 0x400F.F000
Offset 0x504
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
CHIS[n]
R/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CType
0000000000000000Reset
0123456789101112131415
CHIS[n]
R/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CR/W1CType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Channel [n] Interrupt Status
DescriptionValue
The corresponding μDMA channel caused an interrupt.1
The corresponding μDMA channel has not caused an interrupt.0
This bit is cleared by writing a 1 to it.
0x0000.0000R/W1CCHIS[n]31:0
July 24, 2012398
Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
OBSOLETE: TI has discontinued production of this device.