Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500
Each bit of the DMACHASGN register represents the corresponding µDMA channel. Setting a bit
selects the secondary channel assignment as specified in Table 8-1 on page 350.
DMA Channel Assignment (DMACHASGN)
Base 0x400F.F000
Offset 0x500
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
CHASGN[n]
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
CHASGN[n]
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
Channel [n] Assignment Select
DescriptionValue
Use the primary channel assignment.0
Use the secondary channel assignment.1
-R/WCHASGN[n]31:0
397July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.