Table 8-9. Channel Control Structure Offsets for Channel 7 (continued)
DescriptionOffset
Channel 7 Destination End PointerControl Table Base + 0x074
Channel 7 Control WordControl Table Base + 0x078
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Because the peripheral pointer does not change, it simply points to the peripheral's data register.
1. Program the source end pointer at offset 0x070 to the address of the source buffer + 0x3F.
2. Program the destination end pointer at offset 0x074 to the address of the peripheral's transmit
FIFO register.
The control word at offset 0x078 must be programmed according to Table 8-10.
Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example
DescriptionValueBitsField in DMACHCTL
Destination address does not increment331:30DSTINC
8-bit destination data size029:28DSTSIZE
8-bit source address increment027:26SRCINC
8-bit source data size025:24SRCSIZE
Reserved023:18reserved
Arbitrates after 4 transfers217:14ARBSIZE
Transfer 64 items6313:4XFERSIZE
N/A for this transfer type03NXTUSEBURST
Use Basic transfer mode12:0XFERMODE
Note: In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 4, the arbitration size is set to
4. If the peripheral does make a burst request, then 4 bytes are transferred, which is what
the FIFO can accommodate. If the peripheral makes a single request (if there is any space
in the FIFO), then one byte is transferred at a time. If it is important to the application that
transfers only be made in bursts, then the Channel Useburst SET[7] bit should be set in
the DMA Channel Useburst Set (DMAUSEBURSTSET) register.
8.3.3.3 Start the Transfer
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 7 of the DMA Channel Enable Set (DMAENASET) register.
The μDMA controller is now configured for transfer on channel 7. The controller makes transfers to
the peripheral whenever the peripheral asserts a μDMA request. The transfers continue until the
entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller disables
the channel and sets the XFERMODE field of the channel control word to 0 (Stopped). The status of
the transfer can be checked by reading bit 7 of the DMA Channel Enable Set (DMAENASET)
register. This bit is automatically cleared when the transfer is complete. The status can also be
checked by reading the XFERMODE field of the channel control word at offset 0x078. This field is
automatically cleared at the end of the transfer.
July 24, 2012366
Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
OBSOLETE: TI has discontinued production of this device.
