■ Interrupt on transfer completion, with a separate interrupt per channel
8.1 Block Diagram
Figure 8-1. μDMA Block Diagram
System Memory
CH Control Table
Transfer Buffers
Used by µDMA
uDMA
Controller
•
•
•
DMASRCENDP
DMADSTENDP
DMACHCTRL
DMASRCENDP
DMADSTENDP
DMACHCTRL
DMA error
Peripheral
DMA Channel 0
Peripheral
DMA Channel N-1
•
•
•
DMASTAT
DMACFG
DMACTLBASE
DMAALTBASE
DMAWAITSTAT
DMASWREQ
DMAUSEBURSTSET
DMAUSEBURSTCLR
DMAREQMASKSET
DMAREQMASKCLR
DMAENASET
DMAENACLR
DMAALTSET
DMAALTCLR
DMAPRIOSET
DMAPRIOCLR
DMAERRCLR
request
done
request
done
General
Peripheral N
Registers
Nested
Vectored
Interrupt
Controller
(NVIC)
ARM
Cortex-M3
IRQ
request
done
DMACHASGN
DMACHIS
8.2 Functional Description
The μDMA controller is a flexible and highly configurable DMA controller designed to work efficiently
with the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address
increment schemes, multiple levels of priority among DMA channels, and several transfer modes
to allow for sophisticated programmed data transfers. The μDMA controller's usage of the bus is
always subordinate to the processor core, so it never holds up a bus transaction by the processor.
Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth
it provides is essentially free, with no impact on the rest of the system. The bus architecture has
been optimized to greatly enhance the ability of the processor core and the μDMA controller to
efficiently share the on-chip bus, thus improving performance. The optimizations include RAM
striping and peripheral bus segmentation, which in many cases allow both the processor core and
the μDMA controller to access the bus and perform simultaneous data transfers.
The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash
memory and ROM are located on a separate internal bus, it is not possible to transfer data from the
Flash memory or ROM with the μDMA controller.
Each peripheral function that is supported has a dedicated channel on the μDMA controller that can
be configured independently. The μDMA controller implements a unique configuration method using
channel control structures that are maintained in system memory by the processor. While simple
transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that
allow the μDMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part
of a single transfer request. The μDMA controller also supports the use of ping-pong buffering to
accommodate constant streaming of data to or from a peripheral.
349July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
