Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the Flash memory controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AMASKPMASKreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:2
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the interrupt controller.
DescriptionValue
An interrupt is sent to the interrupt controller when the PRIS bit
is set.
1
The PRIS interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WPMASK1
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
interrupt controller.
DescriptionValue
An interrupt is sent to the interrupt controller when the ARIS bit
is set.
1
The ARIS interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WAMASK0
319July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.