Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources. Bits in this
register are the AND of the corresponding bits in the HIBRIS and HIBIM registers. When both
corresponding bits are set, the bit in this register is set, and the interrupt is sent to the interrupt
controller.
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCALT0RTCALT1LOWBATEXTWreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
External Wake-Up Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to a WAKE pin
assertion.
1
An external wake-up interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.
0ROEXTW3
Low Battery Voltage Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to a low battery voltage
condition.
1
A low battery voltage interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.
0ROLOWBAT2
RTC Alert 1 Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to an RTC match.1
An RTC match interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the RTCALT1 bit in the HIBIC register.
0RORTCALT11
July 24, 2012298
Texas Instruments-Production Data
Hibernation Module
OBSOLETE: TI has discontinued production of this device.