Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources. Each bit in
this register masks the corresponding bit in the Hibernation Raw Interrupt Status (HIBRIS) register.
If a bit is unmasked, the interrupt is sent to the interrupt controller. If the bit is masked, the interrupt
is not sent to the interrupt controller.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCALT0RTCALT1LOWBATEXTWreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
External Wake-Up Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the EXTW bit
in the HIBRIS register is set.
1
The EXTW interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WEXTW3
Low Battery Voltage Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the LOWBAT
bit in the HIBRIS register is set.
1
The LOWBAT interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WLOWBAT2
RTC Alert 1 Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the RTCALT1
bit in the HIBRIS register is set.
1
The RTCALT1 interrupt is suppressed and not sent to the
interrupt controller.
0
0R/WRTCALT11
July 24, 2012294
Texas Instruments-Production Data
Hibernation Module
OBSOLETE: TI has discontinued production of this device.
