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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
  • LM3S6G65-IQC80-A2T PDF在线浏览
功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module. This register must be written last
before a hibernate event is issued. Writes to other registers after the HIBREQ bit is set are not
guaranteed to complete before hibernation is entered.
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x8000.0000
16171819202122232425262728293031
reservedWRC
ROROROROROROROROROROROROROROROROType
0000000000000001Reset
0123456789101112131415
RTCENHIBREQCLKSELRTCWENPINWEN
LOWBATEN
CLK32ENVABORTVDD3ONreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Write Complete/Capable
DescriptionValue
The interface is processing a prior write and is busy. Any write
operation that is attempted while WRC is 0 results in
undetermined behavior.
0
The interface is ready to accept a write.1
Software must poll this bit between write requests and defer writes until
WRC=1 to ensure proper operation.
The bit name WRC means "Write Complete," which is the normal use of
the bit (between write accesses). However, because the bit is set
out-of-reset, the name can also mean "Write Capable" which simply
indicates that the interface may be written to by software. This difference
may be exploited by software at reset time to detect which method of
programming is appropriate: 0 = software delay loops required; 1 = WRC
paced available.
1ROWRC31
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved30:9
VDD Powered
DescriptionValue
The internal switches control the power to the on-chip modules
(VDD3ON mode).
1
The internal switches are not used. The HIB signal should be
used to control an external switch or regulator.
0
Note that regardless of the status of the VDD3ON bit, the HIB signal is
asserted during Hibernate mode. Thus, when VDD3ON is set, the HIB
signal should not be connected to the 3.3V regulator, and the 3.3V power
source should remain connected.
0R/WVDD3ON8
291July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
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