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    LM3S6G65-IQC80-A2T

    LM3S6G65-IQC80-A2T首页预览图
    型号： LM3S6G65-IQC80-A2T
    PDF文件：
    • LM3S6G65-IQC80-A2T PDF文件
    • LM3S6G65-IQC80-A2T PDF在线浏览
    功能描述： Stellaris® LM3S6G65 Microcontroller
    PDF文件大小： 6152.12 Kbytes
    PDF页数： 共1044页
    制造商： TI1[Texas Instruments]
    制造商LOGO： TI1[Texas Instruments] LOGO
    制造商网址： http://www.ti.com
    捡单宝LM3S6G65-IQC80-A2T
    PDF页面索引
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    120%
    Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C
    This register is used to load a 32-bit value loaded into the RTC counter. The load occurs immediately
    upon this register being written.
    Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
    Hibernation module clock domain and have special timing requirements. Software should
    make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
    elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
    Timing” on page 278.
    Hibernation RTC Load (HIBRTCLD)
    Base 0x400F.C000
    Offset 0x00C
    Type R/W, reset 0xFFFF.FFFF
    16171819202122232425262728293031
    RTCLD
    R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
    1111111111111111Reset
    0123456789101112131415
    RTCLD
    R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
    1111111111111111Reset
    DescriptionResetTypeNameBit/Field
    RTC Load
    A write loads the current value into the RTC counter (RTCC).
    A read returns the 32-bit load value.
    0xFFFF.FFFFR/WRTCLD31:0
    July 24, 2012290
    Texas Instruments-Production Data
    Hibernation Module
    OBSOLETE: TI has discontinued production of this device.
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