■ Using the VDD3ON mode, where V
DD
continues to be powered in hibernation, allowing the GPIO
pins to retain their states, as shown in Figure 6-3 on page 280. In this mode, V
DDC
is powered off
internally.
■ Using separate sources for V
DD
and V
BAT
, as shown in Figure 6-2 on page 280.
■ Using a regulator to provide both V
DD
and V
BAT
with a switch enabled by HIB to remove V
DD
during hibernation.
Adding external capacitance to the V
BAT
supply reduces the accuracy of the low-battery measurement
and should be avoided if possible. The diagrams referenced in this section only show the connection
to the Hibernation pins and not to the full system.
If the application does not require the use of the Hibernation module, refer to “Connections for
Unused Signals” on page 977. In this situation, the HIB bit in the Run Mode Clock Gating Control
Register 0 (RCGC0) register must be cleared, disabling the system clock to the Hibernation module
and Hibernation module registers are not accessible.
6.3.4 Battery Management
Important: System-level factors may affect the accuracy of the low battery detect circuit. The
designer should consider battery type, discharge characteristics, and a test load during
battery voltage measurements.
The Hibernation module can be independently powered by a battery or an auxiliary power source
using the VBAT pin. The module can monitor the voltage level of the battery and detect when the
voltage drops below V
LOWBAT
. The module can also be configured so that it does not go into Hibernate
mode if the battery voltage drops below this threshold. Battery voltage is not measured while in
Hibernate mode.
The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN
bit of the HIBCTL register. In this configuration, the LOWBAT bit of the Hibernation Raw Interrupt
Status (HIBRIS) register is set when the battery level is low. If the VABORTbit in the HIBCTL register
is also set, then the module is prevented from entering Hibernate mode when a low battery is
detected. The module can also be configured to generate an interrupt for the low-battery condition
(see “Interrupts and Status” on page 283).
Note that the Hibernation module draws power from whichever source (V
BAT
or V
DD
) has the higher
voltage. Therefore, it is important to design the circuit to ensure that V
DD
is higher that V
BAT
under
nominal conditions or else the Hibernation module draws power from the battery even when V
DD
is
available.
6.3.5 Real-Time Clock
The Hibernation module includes a 32-bit counter that increments once per second with the proper
configuration (see “Hibernation Clock Source” on page 279). The 32.768-kHz clock signal, either
directly from the 32.768-kHz oscillator or from the 4.194304-MHz crystal divided by 128, is fed into
a predivider register that counts down the 32.768-kHz clock ticks to achieve a once per second
clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock source
by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and
is used for one second out of every 64 seconds to divide the input clock. This configuration allows
the software to make fine corrections to the clock rate by adjusting the predivider trim register up
or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down
the RTC rate and down from 0x7FFF in order to speed up the RTC rate.
281July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
