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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
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功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
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120%
Table 6-2. Hibernate Signals (108BGA)
DescriptionBuffer Type
a
Pin TypePin Mux / Pin
Assignment
Pin NumberPin Name
An output that indicates the processor is in
Hibernate mode.
ODOfixedM12HIB
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
Power-fixedL12VBAT
An external input that brings the processor out of
Hibernate mode when asserted.
TTLIfixedM10WAKE
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a 4.194304-MHz crystal or a 32.768-kHz
oscillator for the Hibernation module RTC. See the
CLKSEL bit in the HIBCTL register.
AnalogIfixedK11XOSC0
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
AnalogOfixedK12XOSC1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
6.3 Functional Description
The Hibernation module provides two mechanisms for power control:
The first mechanism controls the power to the microcontroller with a control signal (HIB) that
signals an external voltage regulator to turn on or off.
The second mechanism uses internal switches to control power to the Cortex-M3 as well as to
most analog and digital functions while retaining I/O pin power (VDD3ON mode).
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (V
DD
) or the battery/auxilliary voltage
source (V
BAT
). The Hibernation module also has an independent clock source to maintain a real-time
clock (RTC) when the system clock is powered down.
Once in hibernation, the module signals an external voltage regulator to turn the power back on
when an external pin (WAKE) is asserted or when the internal RTC reaches a certain value. The
Hibernation module can also detect when the battery voltage is low and optionally prevent hibernation
when this occurs.
When waking from hibernation, the HIB signal is deasserted. The return of V
DD
causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (t
WAKE_TO_HIB
) plus the power-on reset time (T
IRPOR
).
6.3.1 Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is t
HIB_REG_ACCESS
, therefore
software must guarantee that this delay is inserted between back-to-back writes to certain Hibernation
registers or between a write followed by a read to those same registers. Software may make use
of the WRC bit in the Hibernation Control (HIBCTL) register to ensure that the required timing gap
has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to
software that another write or read may be started safely. Software should poll HIBCTL for WRC=1
prior to accessing any affected register. The following registers are subject to this timing restriction:
July 24, 2012278
Texas Instruments-Production Data
Hibernation Module
OBSOLETE: TI has discontinued production of this device.
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