Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
16171819202122232425262728293031
ADC0ADC1reservedPWMreservedWDT1reserved
R/WR/WROROR/WROROROROROROROR/WROROROType
0000000000000000Reset
0123456789101112131415
reservedWDT0reservedHIBreserved
ROROROR/WROROR/WROROROROROROROROROType
0000001000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:29
WDT1 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 1. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
0R/WWDT128
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27:21
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0R/WPWM20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19:18
July 24, 2012252
Texas Instruments-Production Data
System Control
OBSOLETE: TI has discontinued production of this device.
