Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields, as shown in Table 5-9, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.
Table 5-9. RCC2 Fields that Override RCC Fields
Overrides RCC FieldRCC2 Field...
SYSDIV, bits[26:23]SYSDIV2, bits[28:23]
PWRDN, bit[13]PWRDN2, bit[13]
BYPASS, bit[11]BYPASS2, bit[11]
OSCSRC, bits[5:4]OSCSRC2, bits[6:4]
Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the
RCC register is required, include another register access after writing the RCC register
and before writing the RCC2 register.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x07C0.6810
16171819202122232425262728293031
reserved
SYSDIV2LSB
SYSDIV2
reserved
DIV400USERCC2
ROROROROROROR/WR/WR/WR/WR/WR/WR/WROR/WR/WType
0000001111100000Reset
0123456789101112131415
reservedOSCSRC2reservedBYPASS2
reserved
PWRDN2reserved
ROROROROR/WR/WR/WROROROROR/WROR/WROROType
0000100000010100Reset
DescriptionResetTypeNameBit/Field
Use RCC2
DescriptionValue
The RCC2 register fields override the RCC register fields.1
The RCC register fields are used, and the fields in RCC2 are
ignored.
0
0R/WUSERCC231
Divide PLL as 400 MHz vs. 200 MHz
This bit, along with the SYSDIV2LSB bit, allows additional frequency
choices.
DescriptionValue
Append the SYSDIV2LSB bit to the SYSDIV2 field to create a
7 bit divisor using the 400 MHz PLL output, see Table
5-7 on page 187.
1
Use SYSDIV2 as is and apply to 200 MHz predivided PLL
output. See Table 5-6 on page 186 for programming guidelines.
0
0R/WDIV40030
July 24, 2012212
Texas Instruments-Production Data
System Control
OBSOLETE: TI has discontinued production of this device.
