DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1ROreserved12
PLL Bypass
DescriptionValue
The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV.
1
The system clock is the PLL output clock divided by the divisor
specified by SYSDIV.
0
See Table 5-5 on page 186 for programming guidelines.
Note: The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
1R/WBYPASS11
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below. Depending on the crystal used,
the PLL frequency may not be exactly 400 MHz, see Table
23-8 on page 987 for more information.
Crystal Frequency (MHz) Using
the PLL
Crystal Frequency (MHz) Not
Using the PLL
Value
reserved1.000 MHz0x00
reserved1.8432 MHz0x01
reserved2.000 MHz0x02
reserved2.4576 MHz0x03
3.579545 MHz0x04
3.6864 MHz0x05
4 MHz0x06
4.096 MHz0x07
4.9152 MHz0x08
5 MHz0x09
5.12 MHz0x0A
6 MHz (reset value)0x0B
6.144 MHz0x0C
7.3728 MHz0x0D
8 MHz0x0E
8.192 MHz0x0F
10.0 MHz0x10
12.0 MHz0x11
12.288 MHz0x12
13.56 MHz0x13
14.31818 MHz0x14
16.0 MHz0x15
16.384 MHz0x16
0x0BR/WXTAL10:6
207July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.