DescriptionResetTypeNameBit/Field
Enable System Clock Divider
DescriptionValue
The system clock divider is the source for the system clock. The
system clock divider is forced to be used when the PLL is
selected as the source.
If the USERCC2bit in the RCC2 register is set, then the SYSDIV2
field in the RCC2 register is used as the system clock divider
rather than the SYSDIV field in this register.
1
The system clock is used undivided.0
0R/WUSESYSDIV22
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved21
Enable PWM Clock Divisor
DescriptionValue
The PWM clock divider is the source for the PWM clock.1
The system clock is the source for the PWM clock.0
Note that when the PWM divisor is used, it is applied to the clock for
both PWM modules.
0R/WUSEPWMDIV20
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. The rising
edge of this clock is synchronous with the system clock.
DivisorValue
/20x0
/40x1
/80x2
/160x3
/320x4
/640x5
/640x6
/64 (default)0x7
0x7R/WPWMDIV19:17
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved16:14
PLL Power Down
DescriptionValue
The PLL is powered down. Care must be taken to ensure that
another clock source is functioning and that the BYPASS bit is
set before setting this bit.
1
The PLL is operating normally.0
1R/WPWRDN13
July 24, 2012206
Texas Instruments-Production Data
System Control
OBSOLETE: TI has discontinued production of this device.
