Register 16: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 223
Register 17: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 224
Register 18: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 226
Register 19: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 228
Register 20: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 231
Register 21: Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 233
Register 22: Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 235
Register 23: Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 236
Register 24: Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 240
Register 25: Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 243
Register 26: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 245
Register 27: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 246
Register 28: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 249
Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 252
Register 30: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 254
Register 31: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 257
Register 32: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 260
Register 33: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 263
Register 34: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 265
Register 35: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 267
Register 36: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 269
Register 37: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 271
Register 38: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 274
Hibernation Module ..................................................................................................................... 276
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 287
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 288
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 289
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 290
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 291
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 294
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 296
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 298
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 300
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 301
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 302
Internal Memory ........................................................................................................................... 303
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 313
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 314
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 315
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 318
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 319
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 320
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 321
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 322
Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 323
Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 324
Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 325
Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 326
July 24, 201220
Texas Instruments-Production Data
Table of Contents
OBSOLETE: TI has discontinued production of this device.