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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
  • LM3S6G65-IQC80-A2T PDF在线浏览
功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
5.2.6.4 Hibernate Mode
In this mode, the power supplies are turned off to the main part of the microcontroller and only the
Hibernation module's circuitry is active. An external wake event or RTC event is required to bring
the microcontroller back to Run mode. The Cortex-M3 processor and peripherals outside of the
Hibernation module see a normal "power on" sequence and the processor starts running code.
Software can determine if the microcontroller has been restarted from Hibernate mode by inspecting
the Hibernation module registers. For more information on the operation of Hibernate mode, see
“Hibernation Module” on page 276.
5.3 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register, thereby configuring the microcontroller to run off a "raw" clock source
and allowing for the new PLL configuration to be validated before switching the system clock
to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
5.4 Register Map
Table 5-8 on page 191 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 303.
Table 5-8. System Control Register Map
See
page
DescriptionResetTypeNameOffset
194Device Identification 0-RODID00x000
221Device Identification 1-RODID10x004
223Device Capabilities 00x00FF.00BFRODC00x008
224Device Capabilities 1-RODC10x010
226Device Capabilities 20x030F.5317RODC20x014
191July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
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