Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their Run mode conguration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or ash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
5.2.6.1 Run Mode
In Run mode, the microcontroller actively executes code. Run mode provides normal operation of
the processor and all of the peripherals that are currently enabled by the RCGCn registers. The
system clock can be any of the available clock sources including the PLL.
5.2.6.2 Sleep Mode
In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and
the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered
by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction. Any properly configured
interrupt event in the system brings the processor back into Run mode. See “Power
Management” on page 91 for more details.
Peripherals are clocked that are enabled in the SCGCn registers when auto-clock gating is enabled
(see the RCC register) or the RCGCn registers when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
5.2.6.3 Deep-Sleep Mode
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered on
request from the code. Deep-Sleep mode is entered by first setting the SLEEPDEEP bit in the System
Control (SYSCTRL) register (see page 134) and then executing a WFI instruction. Any properly
configured interrupt event in the system brings the processor back into Run mode. See “Power
Management” on page 91 for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked in Deep-Sleep mode.
Peripherals are clocked that are enabled in the DCGCn registers when auto-clock gating is enabled
(see the RCC register) or the RCGCn registers when auto-clock gating is disabled. The system
clock source is specified in the DSLPCLKCFG register. When the DSLPCLKCFG register is used,
the internal oscillator source is powered up, if necessary, and other clocks are powered down. If
the PLL is running at the time of the WFI instruction, hardware powers the PLL down and overrides
the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting
in the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep
mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the
PIOSC is used as the PLL reference clock source, it may continue to provide the clock during
Deep-Sleep. See page 216.
July 24, 2012190
Texas Instruments-Production Data
System Control
OBSOLETE: TI has discontinued production of this device.
