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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
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功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
StellarisWare Parameter
a
Frequency (BYPASS2=1)Frequency
(BYPASS2=0)
DivisorSYSDIV2
SYSCTL_SYSDIV_64Clock source frequency/643.125 MHz/640x3F
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along
with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In
this situation, the divisor is equivalent to the (SYSDIV2encoding with SYSDIV2LSB appended) plus
one. Table 5-7 shows the frequency choices when DIV400 is set. When the DIV400 bit is clear,
SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table
5-6 on page 186.
Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1
StellarisWare Parameter
b
Frequency (BYPASS2=0)
a
DivisorSYSDIV2LSBSYSDIV2
-reserved/2reserved0x00
-reserved/30
0x01
-reserved/41
SYSCTL_SYSDIV_2_580 MHz/50
0x02
SYSCTL_SYSDIV_366.67 MHz/61
-reserved/70
0x03
SYSCTL_SYSDIV_450 MHz/81
SYSCTL_SYSDIV_4_544.44 MHz/90
0x04
SYSCTL_SYSDIV_540 MHz/101
...............
SYSCTL_SYSDIV_63_53.15 MHz/1270
0x3F
SYSCTL_SYSDIV_643.125 MHz/1281
a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0.
b. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
5.2.5.3 Precision Internal Oscillator Operation (PIOSC)
The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC
must remain enabled as it is used for internal functions. The PIOSC can only be disabled during
Deep-Sleep mode. It can be powered down by setting the IOSCDIS bit in the RCC register.
The PIOSC generates a 16-MHz clock with a ±1% accuracy at room temperatures. Across the
extended temperature range, the accuracy is ±3%. At the factory, the PIOSC is set to 16 MHz at
room temperature, however, the frequency can be trimmed for other voltage or temperature conditions
using software in one of three ways:
Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator
Calibration (PIOSCCAL) register.
User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As
the UT value increases, the generated period increases. To commit a new UT value, first set the
187July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
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