is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-4 on page 183.
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field
StellarisWare
®
Parameter
a
Frequency (BYPASS=1)Frequency (BYPASS=0)DivisorSYSDIV
SYSCTL_SYSDIV_1
b
Clock source frequency/2reserved/10x0
SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x1
SYSCTL_SYSDIV_3Clock source frequency/366.67 MHz/30x2
SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x3
SYSCTL_SYSDIV_5Clock source frequency/540 MHz/50x4
SYSCTL_SYSDIV_6Clock source frequency/633.33 MHz/60x5
SYSCTL_SYSDIV_7Clock source frequency/728.57 MHz/70x6
SYSCTL_SYSDIV_8Clock source frequency/825 MHz/80x7
SYSCTL_SYSDIV_9Clock source frequency/922.22 MHz/90x8
SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x9
SYSCTL_SYSDIV_11Clock source frequency/1118.18 MHz/110xA
SYSCTL_SYSDIV_12Clock source frequency/1216.67 MHz/120xB
SYSCTL_SYSDIV_13Clock source frequency/1315.38 MHz/130xC
SYSCTL_SYSDIV_14Clock source frequency/1414.29 MHz/140xD
SYSCTL_SYSDIV_15Clock source frequency/1513.33 MHz/150xE
SYSCTL_SYSDIV_16Clock source frequency/1612.5 MHz (default)/160xF
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 5-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 5-4 on page 183.
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
StellarisWare Parameter
a
Frequency (BYPASS2=1)Frequency
(BYPASS2=0)
DivisorSYSDIV2
SYSCTL_SYSDIV_1
b
Clock source frequency/2reserved/10x00
SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x01
SYSCTL_SYSDIV_3Clock source frequency/366.67 MHz/30x02
SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x03
SYSCTL_SYSDIV_5Clock source frequency/540 MHz/50x04
...............
SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x09
...............
July 24, 2012186
Texas Instruments-Production Data
System Control
OBSOLETE: TI has discontinued production of this device.