Figure 5-5. Main Clock Tree
Main OSC
Precision
Internal OSC
(16 MHz)
Internal OSC
(30 kHz)
÷ 4
÷ 25
PWRDN
ADC Clock
System Clock
MOSCDIS
a
IOSCDIS
a
SYSDIV
e
USESYSDIV
a,d
PWMDW
a
USEPWMDIV
a
PWM Clock
Hibernation
OSC
(32.768 kHz)
OSCSRC
b,d
BYPASS
b,d
XTAL
a
PWRDN
b
÷ 2
USB PLL
(480 MHz)
÷ 4
USB Clock
XTAL
a
USBPWRDN
c
RXINT
RXFRAC
I
2
S Receive MCLK
I
2
S Transmit MCLK
PLL
(400 MHz)
TXINT
TXFRAC
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2 bit, or
[SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set.
DIV400
c
Note: The figure above shows all features available on all Stellaris® Firestorm-class microcontrollers. Not all peripherals
may be available on this device.
Using the SYSDIV and SYSDIV2 Fields
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASSbit in this register
185July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
