Table 5-3. Reset Sources (continued)
On-Chip Peripherals Reset?JTAG Reset?Core Reset?Reset Source
NoNoYesSoftware System Request
Reset using the VECTRESET
bit in the APINT register.
Yes
a
YesNoSoftware Peripheral Reset
YesYesYesWatchdog Reset
YesYesYesMOSC Failure Reset
a. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, in which case, all the bits in the RESC register are cleared except for the POR indicator.
A bit in the RESC register can be cleared by writing a 0.
At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM
Boot Loader or the application in Flash memory by using any GPIO signal as configured in the Boot
Configuration (BOOTCFG) register.
At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always
executed. The boot sequence executed from ROM is as follows:
1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is
mapped to address 0x0.
2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is
compared with the specified polarity. If the status matches the specified polarity, the ROM is
mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader.
3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and
if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and
execution continues out of the ROM Boot Loader.
4. If there is valid data at address 0x0000.0004, the stack pointer (SP) is loaded from Flash memory
at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004.
The user application begins executing.
For example, if the BOOTCFG register is written and committed with the value of 0x0000.3C01,
then PB7 is examined at reset to determine if the ROM Boot Loader should be executed. If PB7 is
Low, the core unconditionally begins executing the ROM boot loader. If PB7 is High, then the
application in Flash memory is executed if the reset vector at location 0x0000.0004 is not
0xFFFF.FFFF. Otherwise, the ROM boot loader is executed.
5.2.2.3 Power-On Reset (POR)
The internal Power-On Reset (POR) circuit monitors the power supply voltage (V
DD
) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (V
TH
). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete (see “Power and Brown-Out” on page 984). For
applications that require the use of an external reset signal to hold the microcontroller in reset longer
than the internal POR, the RST input may be used as discussed in “External RST Pin” on page 178.
The Power-On Reset sequence is as follows:
177July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
