DescriptionResetTypeNameBit/Field
MPU Default Region
This bit enables privileged software access to the default memory map.
DescriptionValue
If the MPU is enabled, this bit disables use of the default memory
map. Any memory access to a location not covered by any
enabled region causes a fault.
0
If the MPU is enabled, this bit enables use of the default memory
map as a background region for privileged software accesses.
1
When this bit is set, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this default
map.
If the MPU is disabled, the processor ignores this bit.
0R/WPRIVDEFEN2
MPU Enabled During Faults
This bit controls the operation of the MPU during hard fault, NMI, and
FAULTMASK handlers.
DescriptionValue
The MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit.
0
The MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.
1
When the MPU is disabled and this bit is set, the resulting behavior is
unpredictable.
0R/WHFNMIENA1
MPU Enable
DescriptionValue
The MPU is disabled.0
The MPU is enabled.1
When the MPU is disabled and the HFNMIENA bit is set, the resulting
behavior is unpredictable.
0R/WENABLE0
July 24, 2012156
Texas Instruments-Production Data
Cortex-M3 Peripherals
OBSOLETE: TI has discontinued production of this device.