Table 8-3. Control Structure Memory Map ........................................................................... 353
Table 8-4. Channel Control Structure .................................................................................. 353
Table 8-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 362
Table 8-6. μDMA Interrupt Assignments .............................................................................. 363
Table 8-7. Channel Control Structure Offsets for Channel 30 ................................................ 364
Table 8-8. Channel Control Word Configuration for Memory Transfer Example ...................... 364
Table 8-9. Channel Control Structure Offsets for Channel 7 .................................................. 365
Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 366
Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 367
Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 368
Table 8-13. μDMA Register Map .......................................................................................... 370
Table 9-1. GPIO Pins With Non-Zero Reset Values .............................................................. 409
Table 9-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 409
Table 9-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 410
Table 9-4. GPIO Pad Configuration Examples ..................................................................... 416
Table 9-5. GPIO Interrupt Configuration Example ................................................................ 417
Table 9-6. GPIO Pins With Non-Zero Reset Values .............................................................. 418
Table 9-7. GPIO Register Map ........................................................................................... 418
Table 9-8. GPIO Pins With Non-Zero Reset Values .............................................................. 430
Table 9-9. GPIO Pins With Non-Zero Reset Values .............................................................. 436
Table 9-10. GPIO Pins With Non-Zero Reset Values .............................................................. 438
Table 9-11. GPIO Pins With Non-Zero Reset Values .............................................................. 441
Table 9-12. GPIO Pins With Non-Zero Reset Values .............................................................. 447
Table 10-1. Available CCP Pins ............................................................................................ 462
Table 10-2. General-Purpose Timers Signals (100LQFP) ....................................................... 463
Table 10-3. General-Purpose Timers Signals (108BGA) ......................................................... 464
Table 10-4. General-Purpose Timer Capabilities .................................................................... 465
Table 10-5. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 466
Table 10-6. 16-Bit Timer With Prescaler Configurations ......................................................... 467
Table 10-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 468
Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 468
Table 10-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 470
Table 10-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 471
Table 10-11. Timers Register Map .......................................................................................... 476
Table 11-1. Watchdog Timers Register Map .......................................................................... 511
Table 12-1. ADC Signals (100LQFP) .................................................................................... 535
Table 12-2. ADC Signals (108BGA) ...................................................................................... 536
Table 12-3. Samples and FIFO Depth of Sequencers ............................................................ 537
Table 12-4. Differential Sampling Pairs ................................................................................. 545
Table 12-5. ADC Register Map ............................................................................................. 553
Table 13-1. UART Signals (100LQFP) .................................................................................. 616
Table 13-2. UART Signals (108BGA) .................................................................................... 616
Table 13-3. Flow Control Mode ............................................................................................. 621
Table 13-4. UART Register Map ........................................................................................... 626
Table 14-1. SSI Signals (100LQFP) ...................................................................................... 679
Table 14-2. SSI Signals (108BGA) ........................................................................................ 679
Table 14-3. SSI Register Map .............................................................................................. 690
15July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.