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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
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功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
DescriptionResetTypeNameBit/Field
Stack Bus Fault
DescriptionValue
No bus fault has occurred on stacking for exception entry.0
Stacking for an exception entry has caused one or more bus
faults.
1
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the FAULTADDR register.
This bit is cleared by writing a 1 to it.
0R/W1CBSTKE12
Unstack Bus Fault
DescriptionValue
No bus fault has occurred on unstacking for a return from
exception.
0
Unstacking for a return from exception has caused one or more
bus faults.
1
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
FAULTADDR register.
This bit is cleared by writing a 1 to it.
0R/W1CBUSTKE11
Imprecise Data Bus Error
DescriptionValue
An imprecise data bus error has not occurred.0
A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.
1
When this bit is set, a fault address is not written to the FAULTADDR
register.
This fault is asynchronous. Therefore, if the fault is detected when the
priority of the current process is higher than the bus fault priority, the
bus fault becomes pending and becomes active only when the processor
returns from all higher-priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects that both the IMPRE bit is set and one of the precise fault status
bits is set.
This bit is cleared by writing a 1 to it.
0R/W1CIMPRE10
Precise Data Bus Error
DescriptionValue
A precise data bus error has not occurred.0
A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the
fault.
1
When this bit is set, the fault address is written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
0R/W1CPRECISE9
July 24, 2012148
Texas Instruments-Production Data
Cortex-M3 Peripherals
OBSOLETE: TI has discontinued production of this device.
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