DescriptionResetTypeNameBit/Field
Trap on Divide by 0
This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.
DescriptionValue
Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
0
Trap on divide by 0.1
0R/WDIV04
Trap on Unaligned Access
DescriptionValue
Do not trap on unaligned halfword and word accesses.0
Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
1
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
0R/WUNALIGNED3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2
Allow Main Interrupt Trigger
DescriptionValue
Disables unprivileged software access to the SWTRIG register.0
Enables unprivileged software access to the SWTRIG register
(see page 124).
1
0R/WMAINPEND1
Thread State Control
DescriptionValue
The processor can enter Thread mode only when no exception
is active.
0
The processor can enter Thread mode from any level under the
control of an EXC_RETURN value (see “Exception
Return” on page 89 for more information).
1
0R/WBASETHR0
137July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.