Register 34: System Control (SYSCTRL), offset 0xD10
Note: This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.
System Control (SYSCTRL)
Base 0xE000.E000
Offset 0xD10
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedSLEEPEXITSLEEPDEEPreservedSEVONPEND
reserved
ROR/WR/WROR/WROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:5
Wake Up on Pending
DescriptionValue
Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
0
Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
1
When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.
0R/WSEVONPEND4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
Deep Sleep Enable
DescriptionValue
Use Sleep mode as the low power mode.0
Use Deep-sleep mode as the low power mode.1
0R/WSLEEPDEEP2
July 24, 2012134
Texas Instruments-Production Data
Cortex-M3 Peripherals
OBSOLETE: TI has discontinued production of this device.
