Register 32: Vector Table Offset (VTABLE), offset 0xD08
Note: This register can only be accessed from privileged mode.
The VTABLE register indicates the offset of the vector table base address from memory address
0x0000.0000.
Vector Table Offset (VTABLE)
Base 0xE000.E000
Offset 0xD08
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
OFFSETBASEreserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROType
0000000000000000Reset
0123456789101112131415
reservedOFFSET
ROROROROROROROROROR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:30
Vector Table Base
DescriptionValue
The vector table is in the code memory region.0
The vector table is in the SRAM memory region.1
0R/WBASE29
Vector Table Offset
When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 54
interrupts, the offset must be aligned on a 512-byte boundary.
0x000.00R/WOFFSET28:9
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved8:0
131July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.