DescriptionResetTypeNameBit/Field
Disable Interrupts of Multiple Cycle Instructions
DescriptionValue
No effect.0
Disables interruption of load multiple and store multiple
instructions. In this situation, the interrupt latency of the
processor is increased because any LDM or STM must complete
before the processor can stack the current state and enter the
interrupt handler.
1
0R/WDISMCYC0
July 24, 2012126
Texas Instruments-Production Data
Cortex-M3 Peripherals
OBSOLETE: TI has discontinued production of this device.