Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184
Note: This register can only be accessed from privileged mode.
The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt
54. See Table 2-9 on page 84 for interrupt assignments.
Interrupt 32-54 Clear Enable (DIS1)
Base 0xE000.E000
Offset 0x184
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
INTreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:23
Interrupt Disable
DescriptionValue
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN1
register, disabling interrupt [n].
1
0x00.0000R/WINT22:0
115July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.