Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
Note: This register can only be accessed from privileged mode.
See Table 2-9 on page 84 for interrupt assignments.
Interrupt 0-31 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Interrupt Disable
DescriptionValue
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
1
0x0000.0000R/WINT31:0
July 24, 2012114
Texas Instruments-Production Data
Cortex-M3 Peripherals
OBSOLETE: TI has discontinued production of this device.