Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 103 shows.
Figure 3-1. SRD Use Example
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
Base address of both regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
3.1.4.2 MPU Access Permission Attributes
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 103 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M3 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Stellaris Microcontroller” on page 104 for information on programming the MPU for Stellaris
implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
Other AttributesShareabilityMemory TypeBCSTEX
-ShareableStrongly Ordered00x
a
000b
-ShareableDevice10x
a
000
Outer and inner
write-through. No write
allocate.
Not shareableNormal010000
ShareableNormal011000
Not shareableNormal110000
ShareableNormal111000
Outer and inner
noncacheable.
Not shareableNormal000001
ShareableNormal001001
--Reserved encoding10x
a
001
--Reserved encoding01x
a
001
Outer and inner
write-back. Write and
read allocate.
Not shareableNormal110001
ShareableNormal111001
Nonshared Device.Not shareableDevice00x
a
010
--Reserved encoding10x
a
010
--Reserved encodingx
a
1x
a
010
103July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
