System Control
90 October 8, 2006
Preliminary
Register 28: Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register is used to automatically switch from the main oscillator to the internal oscillator when
entering Deep-Sleep mode. The system clock source is the main oscillator by default. When this
register is set, the internal oscillator is powered up and the main oscillator is powered down. When
the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and
frequency it had at the onset of Deep-Sleep mode.
Bit/Field Name Type Reset Description
31:1 Reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
0 IOSC R/W 0 This field allows an override of the main oscillator when
Deep-Sl eep mode is running. W hen set, th is field forces the
internal oscillator to be the clock source during Deep-Sleep
mode. O therwise, th e main os cillator re mains as the default
system cloc k source.
RO
0
Deep-Sleep Clock Configuration (DSLPCLKCFG)
Offset 0x144
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
IOSC
reserved
reserved