LM3S610 Data Sheet
October 8, 2006 81
Preliminary
19:17 PWMDIV R/W 0x7 PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the
system clock down for use as the timing reference for the
PWM module. This clock is only power 2 divide and rising
edge is synchronous without phase shift from PCLK/HCLK.
16:14 reserved RO 0 Reserved bi ts return an indeterminate value, and should
never be change d.
13 PWRDN R/W 1 PLL Power Down
This bit connects to the PLL PWRDN input. The reset value
of 1 powers down the PLL. S ee Table 6-4 on page 82 for
PLL mode cont rol .
12 OEN R/W 1 PLL Output Enable
This bit specifies whether the PLL output driver is enabled.
If cleared, the driver transmits the PLL clock to the output.
Otherwi se, t he PLL clo ck d oes n ot os cill ate ou ts ide th e PLL
module.
Note: Both PWRDN and OEN must be cleared to run the
PLL.
11 BYPASS R/W 1 PLL Bypass
Choose s w het her th e sy ste m cl oc k is deri ved from th e PLL
output or the OSC source. If set, the clock that drives the
system is th e OSC source. Otherwise, the clock that drives
the system is the PLL output clock divided by the system
divider.
Note: The ADC module cannot be used when the PLL is
in Bypass mode (BYPASS set to 1).
10 PLLVER R/W 0 PLL Verification
This bit controls the PLL verification timer function. If set,
the verification timer is enabled and an interrupt is
generated if the PLL becomes inoperative. Otherwise, the
verification timer is not enabled.
Bit/Field Name Type Reset Description
Value Divisor
000 /2
001 /4
010 /8
011 /16
100 /32
101 /64
110 /64
111 /64 (default)