LM3S610 Data Sheet
October 8, 2006 77
Preliminary
Register 15: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
registe r (see page 74).
Bit/Field Name Type Reset Description
31:7 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
6 PLLLMIS R/W1C 0 PLL Lock Masked Interrupt Status
This bit is set when the PLL T
READY
timer assert s. The
interrupt is cleared by writing a 1 to this bit.
5 CLMIS R/W1C 0 Current Limit Masked Interrupt Status
This bit is set if the LDO’s CLE output asserts. The interrupt
is cleared by writing a 1 to this bit.
4 IOFMIS R/W1C 0 Internal Oscillator Fault Masked Interrupt Status
This bit is set if an internal oscillator fault is detected. The
interrupt is cleared by writing a 1 to this bit.
3 MOFMIS R/W1C 0 Main Oscillator Fault Masked Interrupt Status
This bit is set if a main oscillator fault is detected. The
interrupt is cleared by writing a 1 to this bit.
2 LDOMIS R/W1C 0 LDO Power Unregula ted Ma sk ed Inte rrup t Statu s
This bit is set if LDO power is unregulated. The interrupt is
cleared by writing a 1 to this bit.
1 BORMIS R/W1C 0 Brown-Out Reset Masked Interrupt Status
This bit is the masked interrupt status for any brown-out
conditions. If set, a brown-out condition was detected. An
interrupt is reported if the BORIM bit in the IMC register is
set and the BORIOR bit in t he PBORCTL registe r is cl eared.
The interrupt is cleared by writing a 1 to this bit.
0 PLLFMIS R/W1C 0 PLL Fault Masked Interrupt Status
This bit is set if a PLL fault is detected (stops oscillating).
The interrupt is cleared by writing a 1 to this bit.
RO
0
Masked Interrupt Status and Clear (MISC)
Offset 0x058
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
reserved
PLLLMISreserved CLMIS IOFMIS MOFMIS
LDOMIS
BORMISPLLFMIS