System Control
72 October 8, 2006
Preliminary
Register 11: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register (see
page 65).
Bit/Field Name Type Reset Description
31:19 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
18 GPTM2 R/W 0 Reset control for General-Purpose Timer module 2.
17 GPTM1 R/W 0 Reset control for General-Purpose Timer module 1.
16 GPTM0 R/W 0 Reset control for General-Purpose Timer module 0.
15:13 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
12 I2C R/W 0 Reset control for the I
2
C units.
11:5 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
4 SSI R/W 0 Reset control for the SSI units.
3:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
1 UART1 R/W 0 Reset control for the UART1 module.
0 UART0 R/W 0 Reset control for the UART0 module.
reserved
reserved reserved reserved
RO
0
Software Reset Control 1 (SRCR1)
Offset 0x044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
RO
0
Reset
Type
000000000000000
RO RO R/W RO RO RO RO RO RO RO R/W RO RO R/W R/W
SSI
GPTM1 GPTM0
I2C UART0
GPTM2
UART1