LM3S610 Data Sheet
October 8, 2006 71
Preliminary
Register 10: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register (see
page 63).
Bit/Field Name Type Reset Description
31:21 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
20 PWM R/W 0 Reset control for the PWM units.
19:17 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
16 ADC R/W 0 Reset control for the ADC units.
15:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
3 WDT R/W 0 Reset control for the Watchdog unit.
2:0 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
reserved
reserved
RO
0
Software Reset Control 0 (SRCR0)
Offset 0x040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO
reserved
WDT
PWM ADC
reserved