LM3S610 Data Sheet
October 8, 2006 69
Preliminary
Register 8: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
15:2 BORTIM R/W 0x1FFF This field specifies the number of internal oscillator clocks
delayed before the BOR outp ut is res am ple d if the BORWT
bit is set.
The width of this field is derived by the t
BOR
width of 500 μs
and the internal oscillator (IOSC) frequency of 15 MHz ±
50%. At +50%, the counter value has to exceed 10,000.
1 BORIOR R/W 0 BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the
controller . If set, a reset is signa led . Otherwise, an interru pt
is signaled.
0 BORWT R/W 1 BOR Wait and Check for Noise
This bit speci fies the respon se to a brow n-ou t sign al
assertion. If BORWT is set to 1, the controller waits BORTIM
IOSC periods before resampling the BOR output, and if
asserted , it sig nals a BOR co ndi tion in terrupt o r reset. If the
BOR resample is deasserted, the cause of the initial
assertion was likely noise and the interrupt or reset is
suppr essed. I f BORWT is 0, BOR asse rtions do not resamp le
the output and any condition is reported immediately if
enabled.
RO
0
Power-On and Brown-Out Reset Control (PBORCTL)
Offset 0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
R/W
0
Reset
Type
111111111111101
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
BORTIM BORIOR BORWT