LM3S610 Data Sheet
October 8, 2006 63
Preliminary
Register 4: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features.
Bit/Field Name Type Reset Description
31:21 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
20 PWM
a
RO 1 A 1 in this bit indicates the presence of the PWM module.
19:17 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
16 ADC
a
RO 1 A 1 in this bit indicates the presence of the ADC module.
15:12 MINSYSDIV RO 0x03 The reset value is hardware-dependent. A value of 0x03
specifies a 50-MHz CPU clock with a PLL divider of 4.See
the RCC register (page 79) for how to change the system
clock divisor using the SYSDIV bit.
11:8 MAXADCSPD
a
RO 0x2 This field indicates the maximum rate at which the ADC
samples data. A value of 0x2 indicates 500K samples per
second.
7 MPU RO 1 This bit indicates whether the Memory Protection Unit
(MPU) in the Corte x-M3 is avail able. A 0 in this b it indica tes
the MPU is not available; a 1 indicates the MPU is
available.
See the ARM® Cortex™-M3 Technical Reference Manual
for details on the MPU.
6 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
5 TEMP RO 1 This bit specifie s the pres en ce of an inte rnal temperatu r e
sensor.
4 PLL RO 1 A 1 in this bit indicates the presence of an implemented
PLL in the device.
3WDT
a
RO 1 A 1 in this bit indicates a watchdog timer on the device.
RO
0
Device Capabilities 1 (DC1)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000010001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
011001010111111
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
PWM
MAXADCSPD TEMP PLL
reserved ADC
MINSYSDIV WDT
JTAGSWDSWOMPU reserved
reserved