System Control
58 October 8, 2006
Preliminary
6.4 Register Descriptions
The remainder of this section lists and describes the System Control registers, in numerical order
by address offset.
0x044 SRCR1 0x00000000 R/W Software Reset Control 1 72
0x048 SRCR2 0x00000000 R/W Software Reset Control 2 73
0x050 RIS 0x00000000 RO Raw Interrupt Status 74
0x054 IMC 0x00000000 R/W Interrupt Mask Control 75
0x058 MISC 0x00000000 R/W1C Masked Interrupt Status and Clear 77
0x05 C RESC - R/W Reset Cause 78
0x060 RCC 0x078E3AC0 R/W Run-Mode Clock Configuration 79
0x064 PLLCFG - RO XTAL to PLL translation 84
System Control
0x100 RCGC0 0x00000001 R/W Run-Mode Clock Gating Control 0 85
0x104 RCGC1 0x00000000 R/W Run-Mode Clock Gating Control 1 87
0x108 RCGC2 0x00000000 R/W Run-Mode Clock Gating Control 2 89
0x110 SCGC0 0x00000001 R/W Sleep-Mode Clock Gating Control 0 85
0x114 SCGC1 0x00000000 R/W Sleep-Mode Clock Gating Control 1 87
0x118 SCGC2 0x00000000 R/W Sleep-Mode Clock Gating Control 2 89
0x120 DCGC0 0x00000001 R/W Deep-Sleep-Mode Clock Gating Control 0 85
0x124 DCGC1 0x00000000 R/W Deep-Sleep-Mode Clock Gating Control 1 87
0x128 DCGC2 0x00000000 R/W Deep-Sleep-Mode Clock Gating Control 2 89
0X144 DSLPCLKCFG 0x07800000 R/W Deep-Sleep Clock Configuration 90
0x150 CLKVCL R 0x00000 000 R/ W Clock verifi cat ion clear 91
0x160 LDOARST 0x00000000 R/W Allow unregulated LDO to reset the part 92
Table 6-1. System Control Register Map (Sheet 2 of 2)
Offset Name Reset Type Description
See
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