System Control
56 October 8, 2006
Preliminary
two changes above. It is the user's responsibility to have a stable clock source (like the main
oscillator) before the RCC register is switched to use the PLL.
6.1.4.5 Clock Verification Timers
There are three identical clock verification circuits that can be enabled though software. The circuit
checks the faster clock by a slower clock using timers:
The main oscillator checks the PLL.
The main oscillator checks the internal oscillator.
The internal oscillator divided by 64 checks the main oscillator.
If the verification timer function is enabled and a failure is detected, the main clock tree is
immediately switched to a working clock and an interrupt is generated to the controller. Software
can then determine the course of action to take. The actual failure indication and clock switching
does not clear without a write to the CLKVCLR register, an external reset, or a POR reset. The
clock verification timers are controlled by the PLLVER, IOSCVER, and MOSCVER bits in the RCC
registe r (see page 79).
6.1.5 System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registe rs c o ntro l th e cl oc k g ati ng
logic for each peripheral or block in the system while the controller is in Run, Sleep, and
Deep-Sle ep mode, respec tively. The DC1, DC2 and DC4 registers act as a write mask for the
RCGCn, SCGCn, and DCGCn regist ers.
In Run mode, the controller is actively executing code. In Sleep mode, the clocking of the device is
unchanged but the controller no longer executes code (and is no longer clocked). In Deep-Sleep
mode, the clocking of the device may change (depending on the Run mode clock configuration)
and the controller no longer executes code (and is no longer clocked). An interrupt returns the
device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail in this section.
6.1.5.1 Run Mode
Run mode provides normal operation of the processor and all of the peripherals that are currently
enabled by the RCGC n registers. The system clock can be any of the available clock sources
includi ng the PLL .
6.1.5.2 Sleep Mode
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when Auto Clock Gating is
enabled (see RCC register on page 79) or the RCGCn register when the Auto Clock Gating is
disabled. The System Clock has the same source and frequency as that during Run mode.
6.1.5.3 Deep-Sleep Mode
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when Auto Clock Gating is enabled (see RCC
register) or the RCGCn register when the Auto Clock Gating is disabled. The system clock source
is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled (see page 90). When the DSLPCLKCFG register is used, the internal oscillator is
powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the
time of the WFI instruction, hardware powers the PLL down and overrides the SYSDIV field of the
active RCC register to be /16 or /64 respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that were stopped during the Deep-Sleep duration.
