LM3S610 Data Sheet
October 8, 2006 55
Preliminary
Figure 6-2. Main Clock Tree
6.1.4.2 PLL Frequency Configuration
The user does not have direct control over the PLL frequency , but is required to match the external
crystal used to an internal PLL-Crystal table. This table is used to create the best fit for PLL
parameters to the crystal chosen. Not all crystals result in the PLL operating at exactly 200 MHz,
though the freque nc y is within
±1%. The result of the lookup is kept in the XTAL to PLL
Translation (PLLCTL) register (see page 84).
Table 6-4 on page 82 describes the available crystal choices and default programming of the
PLLCTL register. The crystal number is written into the XTAL field of the Run-Mode Clock
Configuration (RCC) register (see page 79). Any time the XTAL field changes, a read of the
internal table is performed to get the correct value. Table 6-4 on page 82 describes the available
crystal choices and default programming values.
6.1.4.3 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
Normal: The PLL multiplies the input clock reference and drives the output.
Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the
output.
The modes are programmed using the RCC register fields as shown in Table 6-4 on page 82.
6.1.4.4 PLL Operation
If the PLL configuration is changed, the PLL output is not stable for a period of time (PLL
T
READY
=0.5 ms) and during this time, the PLL is not usable as a clock reference.
The PLL is changed by one of the following:
Change to the XTAL value in the RCC register (see page 79)—writes of the same value do not
cause a relock.
Change in the PLL from Pow er -D own to Normal mod e.
A counter is defined to measure the T
READY
requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is
set to 0x1200 (that is, ~600
μs at a 8.192-MHz external oscillator clock). Hardware is provided to
keep the PLL from being used as a system clock until the T
READY
condition is met after one of the
Main
Osc
1-8 MHz
Internal
Osc
15 MHz
÷4
OSCSRC
a
OSC1
OSC2
PLL
(200 MHz
output )
BYPASS
a
SYSDIV
a
USESYSDIV
a
Sys tem Clock
Constant
Divide
( 16 .667 M H z output )
ADC Clock
PWMDIV
a
USEPWMDIV
a
PWM Clock
OEN
a
XTAL
a
PWRDN
a
a. These are bit fields within the Run-M ode Clock Configuration (RCC) register.
