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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
System Control
52 October 8, 2006
Preliminary
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The external reset timing is shown in Figure 19-9 on page 388.
6.1.2.3 Power-On Reset (POR)
The Power-On Reset (POR) circuitry detects a rise in power-supply voltage and generates an
on-chip reset pulse. To use the on-chip circuitry, the RST
input needs a pull-up resistor (1K to
10K Ω).
The device must be operating within the specified operating parameters at the point when the
on-chip power-on reset pulse is complete. The specified operating parameters include supply
voltage, frequency, temperature, and so on. If the operating conditions are not met at the point of
POR end, the Stellaris controller does not operate correctly. In this case, the reset must be
extended using external circuitry. The RST
input may be used with the circuit as shown in
Figure 6-1.
Figure 6-1. External Circuitry to Extend Reset
The R
1
and C
1
components define the power-on delay . The R
2
resistor mitigates any leakage from
the RST
input. The diode discharges C
1
rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST
) or internal POR to go inactive.
2. Af ter the resets are inactive, the main crystal oscillator must be allowed to settle and there is
an internal main oscillator counter that takes from 15-30 ms to account for this. During this
time, internal reset to the rest of the controller is held active.
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset
timing is shown in Figure 19-10 on page 388.
6.1.2.4 Brown-Out Reset (BOR)
A dr op in the i npu t vo lta ge re sul tin g in t he asse rtio n of t he i nte rna l bro wn- out de te cto r can b e us ed
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if V
DD
drops below V
BTH
. The
circuit is provided to guard against improper operation of logic and peripherals that operate off V
DD
and not the LDO voltage. If a brown-out condition is detected, the system may generate a
controller interrupt or a system reset. The BOR circuit has a digital filter that protects against
noise-related detection. This feature may be optionally enabled.
R
1
C
1
R
2
RST
Stellaris
D
1
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