LM3S610 Data Sheet
October 8, 2006 45
Preliminary
Figure 5-2. Test Access Port State Machine
5.2.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial
shift register chain samples specific information during the TAP controller’s CAPTURE states and
allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the
sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift
registe r on TDI. This new data is stored in the parallel load register during the TAP controller’s
UPDATE states. Each of the shift registers is discussed in detail in “Shift Registers” on page 45.
5.2.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG
pins can be programmed to be GPIOs, board configuration and reset conditions on these pins
must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes requires clarification.
5.2.4.1 GPIO Functionality
When the controller is reset with either a POR or RST
, the JTAG port pins default to their JTAG
configurations. The default configuration includes enabling the pull-up resistors (setting GPIOPUR
Test Logic
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
111
11
1
11
11
11
11
1100
00
00
00
00
00
00
0
0
