LM3S610 Data Sheet
October 8, 2006 43
Preliminary
5.2.1 JTAG Interf ace Pins
The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 5-1. Detailed information on each pin follows.
5.2.1.1 T est Reset Input (TRST
)
The TRST
pin is an asynchronous active Low input signal for initializing and resetting the JTAG
TAP controller and associated JTAG circuitry. When TRST
is asserted, the T AP controller resets to
the Test-Logic-Reset state and remains there while TRST
is asserted. When the TAP controller
enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default
instruction, IDCODE.
By default, the internal pull-up resistor on the TRST
pin is enabled after reset. Changes to the
pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains
enabled on PB7/TRST
; otherwise JTAG communication could be lost.
5.2.1.2 T est Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP
controllers that are daisy-chained together can synchronously communicate serial test data
between components. During normal operation, TCK is driven by a free-running clock with a
nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of
time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in
the JTAG Instruction and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.3 T est Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is
entered. Bec au se the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1
expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST
. The JTAG Test Access Port state
machine can be seen in its entirety in Figure 5-2 on page 45.
Table 5-1. JTAG Port Pins Reset State
Pin Name
Data
Direction
Internal
Pull-Up
Internal
Pull-Down
Drive
Strength
Drive Value
TRST
Input Enabled Disabled N/A N /A
TCK Input Enabled Disabled N/A N /A
TMS Input Enabled Disabled N/A N /A
TDI Input Enabled Disabled N/A N /A
TDO Output Enabled Disabled 2-mA driver High-Z
