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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
LM3S610 Data Sheet
October 8, 2006 39
Preliminary
Usage Fault 6 sett able Usage fa ult, su ch as undefi ned instru ction execu ted
or illegal state transition attempt. This is
synchronous.
-
7-10
-
Reserved.
SVCall 11 settable System service call with SVC instruction. This is
synchronous.
Debug Monitor 12 settable Debug monitor (when not halting). This is
synchronous, but only active when enabled. It does
not activate if lower priority than the cu rrent
activation.
-
13
-
Reserved.
PendSV 14 settable Pendable request for system service. This is
asynchronous and only pended by software.
SysTick 15 settable System tick timer has fired. This is asynchronous.
Interrupts 16 and
above
sett able Asserted from o utsid e the ARM Cortex
-M3 core and
fed through the NVIC (prioritized). These are all
asynchronous. Table 4-2 lists the interrupts on the
LM3S610 controller.
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Interrupt
(Bit in Interrupt Registers)
Description
0 GPIO Port A
1 GPIO Port B
2 GPIO Port C
3 GPIO Port D
4 GPIO Port E
5UART0
6UART1
7 SSI
8I
2
C
9 PWM Fault
10 PWM Generator 0
11 PWM Generator 1
12 PWM Generator 2
Table 4-1. Exception Types (Continued)
Exception Type Position Priority
a
Description
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